1. Field of the Invention
The present invention relates to a system on a programmable chip. More specifically, the present invention relates to methods and apparatus for a memory controller to share I/O lines associated with a system on a programmable chip.
2. Description of Related Art
Conventional programmable chip systems often include a variety of components on-chip. Integrating a variety of peripheral interfaces and peripheral components on-chip allows efficient implementation of a programmable chip system. However, it is also often desirable to also use off-chip components. Some off-chip components such as memory are inexpensive and readily available and can be used to supplement on-chip components. In some examples, separate independent buses are used to control off-chip components. Each bus could be connected to a different type of memory through a peripheral interface.
However, techniques and mechanisms for integrating off-chip components with on-chip components are limited. For programmable chips interconnected with a large number of off-chip components, conventional interconnection mechanisms are often inadequate.
Consequently, it is therefore desirable to provide improved methods and apparatus for interconnecting on-chip components such as components on a programmable chip to off-chip component such as memory. In one example, it is desirable to provide logic and circuitry to interconnect system on a programmable chip components such buses and input/output lines with a variety of different off-chip components.